1. Field of the Invention
The present invention relates to semiconductor devices and particularly to a semiconductor device having an inductor.
2. Description of the Background Art
SOI (Silicon On Insulator) structure semiconductor devices (hereinafter referred to as SOI devices), which are formed on an SOI substrate having a silicon substrate and a buried oxide film and an SOI layer lying on the silicon substrate, offer reduced parasitic capacitance, stable high-speed operation, and reduced power consumption. The SOI devices are used in portable devices, for example.
Examples of the SOI devices include full trench isolation (FTI) structure SOI devices, in which elements are electrically isolated from each other by a full trench isolation insulating film formed by burying an insulator in a trench that is formed in the surface of the SOI layer to reach the buried oxide film. However, various problems exist due to substrate floating effect, e.g. carries (holes in NMOS) produced by impact ionization accumulate in the channel formation region to cause kinks or deteriorate the operating breakdown voltage, and the unstable potential of the channel formation region causes frequency dependency of delay time.
To solve these problems, partial trench isolation (PTI) structure has been proposed, in which an insulator is buried in a trench that is formed in the surface of the SOI layer in such a way that a given thickness of the SOI layer remains between the trench bottom and the buried oxide film.
Adopting the PTI structure enables carriers to move through the well region under the trench isolation insulating film to prevent the accumulation of carriers in the channel formation region, and makes it possible to fix the potential of the channel formation region through the well region, thus solving various problems due to the substrate floating effect. Such PTI structures are described in Y. Hirano et al., 1999 IEEE International SOI Conference, “Bulk-Layout-Compatible 0.18 μm SOI-CMOS Technology Using Body-Fixed Partial Trench Isolation (PTI)”, pp. 131–132 and S. Maeda et al., 2000 Symposium on VLSI Technology Digest of Technical Papers, “Impact of 0.18 μm SOI CMOS Technology using Hybrid Partial Trench Isolation with High Resistivity Substrate on Embedded RF/Analog Applications”.
However, in an SOI device adopting the PTI structure and having a spiral inductor (an inductance element), if the PTI structure is present under the inductor, the current flowing in the spiral inductor causes eddy current in the SOI layer (silicon layer) between the trench bottom and the buried oxide film, which causes electromagnetic induction loss. This reduces Q value (a value obtained by dividing the energy accumulated in the inductor by various losses) that represents inductor performance. Therefore a full trench isolation insulating film is provided in the entire area of the SOI layer that is located under the spiral inductor, with the PTI structure being absent under the spiral inductor.
Now, the spiral inductor has a rectangular contour having sides of several tens to several hundreds of micrometers. Thus, when a full trench isolation insulating film is formed as mentioned above, a region with no pattern extends over a large area corresponding to the area where the spiral inductor resides.
With such structure, a CMP (Chemical Mechanical Polishing) process for the formation of the full trench isolation insulating film excessively removes the full trench isolation insulating film over a desired amount of polishing, causing the thickness of the full trench isolation oxide to gradually decrease toward the center, i.e. so-called dishing.
In order to prevent the dishing, as described in Japanese Patent Application Laid-Open No. 2002-110908 (6th column, FIGS. 3 and 4), for example, a conventional structure has been proposed in which a plurality of dummy element regions are dispersively arranged under the area where the spiral inductor resides and in the vicinity thereof.
Thus, in an SOI device having a spiral inductor, providing a full trench isolation insulating film in the entire SOI layer area under the spiral inductor causes dishing during the manufacturing process.